The present disclosure herein relates to semiconductor devices and, more particularly, to three dimensional semiconductor memory devices and methods of fabricating the same.
Semiconductor devices may be attractive in the electronics industry because of small size, multi-function and/or low fabrication costs. High performance semiconductor devices and/or low cost semiconductor devices have been increasingly demanded with the development of the electronics industry. The semiconductor devices have been more highly integrated in order to meet the above demands. In particular, to store greater amounts of logic data, the integration density of semiconductor memory devices has been increased.
In two dimensional semiconductor memory devices, a planar area in which a unit memory cell occupies may directly affect the integration density of the two dimensional semiconductor memory devices. That is, the integration density of the two dimensional semiconductor memory devices may be influenced by a minimum feature size which may correspond to a process technology for forming fine patterns. However, there may be limitations in improving the process technology for forming the fine patterns. In addition, high cost equipment or apparatus may be required to form the fine patterns. Thus, cost for fabricating the highly integrated semiconductor memory devices may be increased.
Recently, three dimensional semiconductor memory devices including a plurality of memory cells three dimensionally arrayed have been proposed which may address at least some of the above limitations.